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Hardware and Architecture

The design and organization of computer systems, including processor architecture, memory systems, parallel computing, embedded systems, quantum computing hardware, and energy-efficient computing

6 papers

Papers

Analog in-memory computing attention mechanism for fast and energy-efficient large language models

This paper introduces a novel analog in-memory computing architecture using "gain cells" for the attention mechanism in large language models (LLMs). This hardware approach significantly reduces energy consumption (up to four orders of magnitude) and latency (up to two orders of magnitude) compared to GPUs, achieving GPT-2 comparable performance despite introducing hardware-specific non-idealities and limitations like capacitor leakage. The authors developed an adaptation algorithm to map pre-trained models to this new hardware without training from scratch.

Hardware and Architecture Oct 02, 12:31 PM

Quantum error correction below the surface code threshold

Google's new "Willow" superconducting processor successfully demonstrated below-threshold error correction using surface codes, meaning as the code became more complex, errors decreased exponentially. This resulted in a distance-7 code with a lifetime more than double that of the best physical qubit, showing promise for large-scale fault-tolerant quantum computing. However, rare correlated errors still pose a limit to the achievable fidelity.

Hardware and Architecture Sep 11, 02:10 AM

Improvement of the Natural Self-Timed Circuit Tolerance to Short-Term Soft Errors

This paper explores the inherent tolerance of self-timed circuits to soft errors and suggests methods for enhancement. By treating anti-spacer states as valid spacers and improving pipeline indication, the authors theoretically demonstrate complete masking of soft errors in combinational circuits and increased tolerance in sequential circuits using DICE-like approaches.

Hardware and Architecture Jul 14, 10:32 AM

Gap-enhanced Raman tags for physically unclonable anticounterfeiting labels

This research demonstrates the use of gap-enhanced Raman tags (GERTs) as a robust and highly-encoded physical unclonable function (PUF) for anticounterfeiting labels. By drop-casting different GERTs onto a substrate, a unique, random pattern is created which is nearly impossible to reproduce, offering a high level of security through 3D encoding based on the tags' location, spectral profile, and Raman intensity.

Hardware and Architecture Jul 14, 10:32 AM